This application claims benefit of priority under 35 USC xc2xa7119 to Japanese Patent Application No.2000-87679, filed on Mar. 27, 2000, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention is related generally to a semiconductor integrated circuit making use of standard cells.
2. Prior Art
In the case of the conventional approach to the design of semiconductor integrated circuits making use of standard cells, a plurality of types of standard cells having the same cell height are prepared and arranged in cell rows as part of the integrated circuit. It is, therefore, desirable for the sizes of the respective standard cells to be small in order to realize a higher packing densities of integrated circuits making use of standard cells. However, there occurrs a tradeoff to be made between the cell size and the driving power of the cell when the cell size is decreased by decreasing the size of the constituent transistors. One solution of the shortcomings is disclosed in Japanese Patent Application Hei 11-269484 in which part of a standard cell is shared with an adjacent standard cell in order to virtually reduce the cell size.
FIG. 1 is a schematic diagram showing the configuration of the semiconductor integrated circuit in accordance with the above described conventional technique in which (a) of the same figure is a plan view showing a standard cell constituting a 2-input NAND gate; (b) is a plan view showing a standard cell constituting an inverter; and (c) is a plan view showing the 2-input NAND gate as illustrated in FIG. 1(a) and the inverter as illustrated in FIG. 1(b) which are located adjacent to each other and combined with each other. Meanwhile, in FIG. 1, illustration of metallic wiring layers are dispensed with for the sake of clarity in explanation while illustrating the source regions, polysilicon layers, contact regions and the cell boundary lines (cell box) indicative of the respective cell areas, while illustrating source regions, polysilicon layers, contact regions and a cell boundary line (cell box) indicative of the cell area and the location of the gate electrodes are illustrated with bold lines. Also, not shown in the figure, substrate regions are provided between and shared by cells adjacent to each other in the longitudinal (vertical) direction and arranged in order to form cell rows. A plurality of standard cell rows are arranged in parallel so that a number of standard cells are arranged in the longitudinal and lateral directions and combined with the cell boundary lines as aligned to each other in order to implement predetermined functions.
As illustrated in FIG. 1(a), source regions 105, 106 and 107 are located beyond the cell boundary line 109 as well as part of the contact regions 101, 102 and 103. The source regions 105, 106 and 107 and the contact regions 101, 102 and 103 are located in the both sides of the cell. Also, there is provided a shared region 108 where the source region of an adjacent cell is formed as well as a contact region 104. In the case of the inverter cell as illustrated in FIG. 1(b), the source region 110 and the contact region 111 are located beyond the cell boundary line 114, i.e., located in shared regions. When the NAND circuit as illustrated in FIG. 1(a) and the inverter cell as illustrated in FIG. 1(b) are located adjacent to each other as illustrated in FIG. 1(c), the source region 106 and the contact region 102 of the NAND circuit and the source region 110 and the contact region 111 of the inverter cell are united and shared by the NAND circuit and the inverter cell. The source region 112 inclusive of the contact region 113 as shared by the adjacent cells are formed including a concave area.
Since the source regions and the contact regions thereof are shared by adjacent standard cells, the length of the cell row is decreased in the lateral direction so that the effective size of each standard cell can be reduced.
While the conventional technique is very effective in the case of small-sized cells (i.e., having narrow widths while the standard cells in a cell row have the same height in the longitudinal direction), the advantages is diminished as the size increases. In the case of a standard cell having a certain width, the cell size sometimes becomes smaller by providing private substrate regions than that when the standard cell shares substrate regions with adjacent cells.
In brief, the above and other objects and advantages of the present invention are provided by a new and improved semiconductor integrated circuit including a plurality of standard cells which are arranged adjacent to each other in a cell row and composed of a plurality of MOS transistors, each standard cell of said cell row being provided with at least one first contact region through which at least one of said MOS transistors is electrically connected to a power potential, at least one second contact region through which at least one of said MOS transistors is electrically connected to a ground potential and first and second substrate regions located in upper and lower sides of the standard cell,
wherein said first substrate region is provided with at least one contact region through which said first substrate is electrically connected to said power potential while said second substrate region is provided with at least one contact region through which said second substrate is electrically connected to said ground potential,
wherein said first substrate region of said each standard cell is joined to the first substrate region of an adjacent cell of said cell row located adjacent to said each standard cell in order to form a first continuous region extending along said cell row in parallel while the second substrate region of said each standard cell is joined to the second substrate region of said adjacent cell in order to form a second continuous region extending along said cell row in parallel,
wherein said first contact region of said each standard cell is located beyond the boundary line between said each standard cell and said adjacent cell and shared by said each standard cell and said adjacent cell to function also as the first contact region of said adjacent cell,
wherein said at least one contact region of said first substrate region of said each standard cell is located to be inwardly displaced from the centers of said first substrate region in the longitudinal direction at the location where said first substrate region has a minimum width and functions also as said first contact region of said each standard cell, and
wherein said at least one contact region of said second substrate region of said each standard cell is located to be inwardly displaced from the centers of said second substrate region in the longitudinal direction at the location where said second substrate region has a minimum width and functions also as said second contact region of said each standard cell.
In a preferred embodiment, further improvement resides in that there is a vacant area where no functional cell is arranged in said cell row.
In a preferred embodiment, further improvement resides in that said vacant area is padded with an inoperative cell which causes no operation.
In a preferred embodiment, further improvement resides in that said inoperative cell is provided with a substrate region and a contact region.
In a preferred embodiment, further improvement resides in that the widths of said first and second substrate regions have widths narrower than that as required for forming contact regions thereon under constraints determined by manufacture processes.
In a preferred embodiment, further improvement resides in that the perimeters of said contact regions of said first and second substrate regions are displaced from the center positions of the substrate regions of said first and second substrate regions by an interval no narrower than one half of a minimum allowable interval for complying with mask design rules.
In accordance with another aspect of the present invention, an improved semiconductor integrated circuit includes a plurality of standard cells which are arranged adjacent to each other in a cell row and composed of a plurality of MOS transistors, each standard cell of said cell row being provided with at least one first contact region through which at least one of said MOS transistors is electrically connected to a power potential, at least one second contact region through which at least one of said MOS transistors is electrically connected to a ground potential and first and second substrate regions located in upper and lower sides of the standard cell,
wherein said first substrate region of said each standard cell is joined to the first substrate region of an adjacent cell of said cell row located adjacent to said each standard cell within said each cell row in order to form a first substrate continuous region extending along said cell row in parallel while the second substrate region of said each standard cell is joined to the second substrate region of said adjacent cell in order to form a second substrate continuous region extending along said cell row in parallel,
wherein said first substrate continuous region is provided with a plurality of contact regions through which said first substrate is electrically connected to said power potential while said second substrate continuous region is provided with a plurality of contact regions through which said second substrate is electrically connected to said ground potential,
wherein said first substrate continuous region is provided with a plurality of expanded regions which are extended inwardly toward said standard cells in the longitudinal direction at the location, and
wherein said contact regions of said first substrate continuous region are located in said expanded regions.
In accordance with a further aspect of the present invention, an improved semiconductor integrated circuit includes a plurality of standard cells which are arranged adjacent to each other in a cell row and composed of a plurality of MOS transistors, each standard cell of said cell row being provided with at least one first contact region through which at least one of said MOS transistors is electrically connected to a power potential, at least one second contact region through which at least one of said MOS transistors is electrically connected to a ground potential and first and second substrate regions located in upper and lower sides of the standard cell,
wherein said first substrate region of said each standard cell is joined to the first substrate region of an adjacent cell of said cell row located adjacent to said each standard cell within said each cell row in order to form a first substrate continuous region extending along said cell row in parallel while the second substrate region of said each standard cell is joined to the second substrate region of said adjacent cell in order to form a second substrate continuous region extending along said cell row in parallel,
wherein said first substrate continuous region is provided with a plurality of contact regions through which said first substrate is electrically connected to said power potential while said second substrate continuous region is provided with a plurality of contact regions through which said second substrate is electrically connected to said ground potential,
wherein said first substrate continuous region is provided with a plurality of expanded regions which are extended inwardly toward said standard cells in the longitudinal direction at the location, and
wherein said expanded regions are formed in spaces which said standard cell can afford.